René Cumplido

CCC - INAOE

Publications

2018

• “Compact FPGA hardware architecture for public key encryption in embedded devices”, Luis Rodríguez-Flores, Miguel Morales-Sandoval, René Cumplido, Claudia Feregrino-Uribe, Ignacio Algredo-Badillo, 23 Jan 2018 PLOS ONE, https://doi.org/10.1371/journal.pone.0190939

2017

• “On the design of hardware-software architectures for frequent itemsets mining on data streams”, Martin Letras, Alicia Morales-Reyes, Rene Cumplido. Neurocomputing. Elsevier. Volume 175, Part B, 29 January 2016, Pages 899–910. ISSN: 0925-2312.
• “Improving the construction of ORB through FPGA-based acceleration”,de Lima, R., Martinez-Carranza, J., Morales-Reyes, A., Cumplido, R., Machine Vision and Applications (2017). DOI: doi.org/10.1007/s00138-017-0851-5. ISSN 0932-8092
• “Approximate Frequent Itemsets Mining on Data Streams Using Hashing and Lexicographic Order in Hardware”,Lázaro Bustio-Martínez, René Cumplido, Martín Letras-Luna, Claudia Feregrino Uribe, Raudel Hernández-León, José M. Bande-Serrano, 2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS), February 20-23, Bariloche, Argentina. Pp. 149-152.
• “A Compact FPGA-based Microcoded Coprocessor for Exponnentiation in Asymmetric Encryption”, L. Rodriguez-Flores, Miguel Morales-Sandoval, R. Cumplido, C. Feregrino-Uribe, I. Algredo-Badillo, 2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS), February 20-23, Bariloche, Argentina. Pp. 229-232.

2016

• “A Scalable and Customizable Processor Array for Implementing Cellular Genetic Algorithms”, Lázaro Bustio-Martínez, René Cumplido, Raudel Hernández-León, José M. Bande-Serrano, Claudia Feregrino-Uribe, Journal of Intelligent Information Systems, May 2017, pp. 1-26. ISSN: 0925-9902. DOI 10.1007/s10844-017-0461-8.
• “Frequent Itemsets Mining in Data Streams Using Reconfigurable Hardware”, Lázaro Bustio , René Cumplido, Raudel Hernández, José M. Bande, Claudia Feregrino. New Frontiers in Mining Complex Patterns, Volume 9607, Lecture Notes in Computer Science, pp 32-45, DOI: 10.1007/978-3-319-39315-5_3. Springer International Publishing Switzerland. ISBN 978-3-319-39314-8.
• “An FPGA Architecture to Accelerate the Burrows Wheeler Transform by Using a Linear Sorter”, Juan Andrés Pérez-Celis, José Martínez-Carranza, Alicia Morales-Reyes, Claudia Feregrino-Uribe and René Cumplido. 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 23rd Reconfigurable Architectures Workshop, May 23-24, 2016, Chicago, USA. Pp. 156-161. IEEE Press. DOI 10.1109/IPDPSW.2016.174.
• “Hardware Architectures for Frequent Itemset Mining Based on Equivalence Classes Partitioning”, Martin Letras, Raudel Hernández-León and Rene Cumplido. 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 23rd Reconfigurable Architectures Workshop, May 23-24, 2016, Chicago, USA. Pp. 289-294. IEEE Press. DOI DOI 10.1109/IPDPSW.2016.98

2015

• “Video Watermarking Method Resisant to temporal Desynchronization Attacks", Pedro Aaron Hernandez-Avalos, Claudia Feregrino-Uribe, Rene Cumplido-Parra, Jose Juan Garcia-Hernandez. US Patent 9,087,377. July 21, 2015.
• “An analysis of Computational Models for Accelerating the Subtractive Pixel Adjacency Model Computation” Marisol Rodriguez-Perez, Alicia Morales-Reyes, Rene Cumplido, Claudia Feregrino-Uribe. Computers & Electrical Engineering. Volume 43, April 2015, Pages 9–16. doi:10.1016/j.compeleceng.2015.01.004. ISSN: 0045-7906.
• “Processor arrays generation for matrix algorithms used in embedded platforms implemented on FPGAs”, Roberto Pérez-Andrade, César Torres-Huitzil, René Cumplido. Microprocessors and Microsystems Microprocessors and Microsystems 39 (2015) 576–588. doi:10.1016/j.micpro.2014.12.003. ISSN: 0141-9331.
• “A fast hardware software platform for computing irreducible testors”, Vladimir Rodríguez-Dieza, José Francisco Martínez-Trinidad, Jesús Ariel Carrasco-Ochoa, Manuel Lazo-Cortés, Claudia Feregrino-Uribe, René Cumplido. Expert Systems with Applications, Volume 42, Issue 24, 30 December 2015, Pages 9612–9619. doi:10.1016/j.eswa.2015.07.037. ISSN: 0957-4174.
• “Accelerating the Construction of BRIEF Descriptors Using an FPGA-based Architecture”, Roberto de Lima, Jose Martinez-Carranza, Alicia Morales-Reyes and Rene Cumplido. 2015 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2015), Catálogo IEEE CFP15389-CDR, ISBN 978-1-4673-9405-5.
• “A Hardware Based Approach for Frequent Itemset Mining in Data Streams”, Lázaro Bustio, Raudel Hernández, René Cumplido, Claudia Feregrino, and José M. Bande. New Frontiers in Mining Complex Patterns workshop. Porto Portugal, Sep 7, 2015, in conjunction with ECML-PKDD 2015.
• “An Empirical Analysis on Dimensionality in Cellular Genetic Algorithms”. Alicia Morales, Hugo Jair Escalante, Martin Letras, Rene Cumplido. Proceedings of the 2015 Annual Conference on Genetic and Evolutionary Computation (GECCO), pp. 895-902, Madrid, Spain, July, 11-17, 2015. ACM. DOI: 10.1145/2739480.2754699.

2014

• "An Area Efficient Composed CORDIC Architecture", Aguirre-Ramos, F., Morales-Reyes, A., Feregrino-Uribe, C., Cumplido, R., Advances in Electrical and Computer Engineering, Vol. 14, No. 2, pp. 113-116, May 2014, DOI: 10.4316/AECE.2014.02019.
• “Hardware Architecture for Security Improved Fallahpour Audio Watermarking Scheme”, Claudia Feregrino-Uribe, Ernesto Aparicio-Díaz, José Juan García-Hernández, Alejandra Menendez, René Cumplido, Alicia Morales-Reyes. IEICE Electronics Express, Vol. 11 (2014) No. 9 pp. 20140223. DOI: 10.1587/elex.11.20140223. ONLINE ISSN: 1349-2543.
• “A Node Linkage Approach for Sequential Pattern Mining”, Navarro O, Cumplido R, Villaseñor-Pineda L, Feregrino-Uribe C, Carrasco-Ochoa JA. PLoS ONE 9(6): e95418. June 16, 2014. doi:10.1371/journal.pone.0095418.
• “Synthesizing VHDL from Activity Models in UML 2”, Tomás Balderas Contreras, René Cumplido, Gustavo Rodríguez. Circuit Theory with Applications. Volume 42, Issue 5, pages 542–550, May 2014. ISSN: 1097-007X. DOI: 10.1002/cta.1874.
• “A compact FPGA-based processor for the Secure Hash Algorithm SHA-256”, R. García, I. Algredo-Badillo, M. Morales-Sandoval, C. Feregrino-Uribe, R. Cumplido. Volume 40, Issue 1, January 2014, Pages 194–202. 40th-year commemorative issue. Computers & Electrical Engineering. DOI: 10.1016/j.compeleceng.2013.11.014.
• “The Evaluation of Ordered Features for SMS Spam Filtering”, José M. Bande Serrano, José Hernández Palancar, René Cumplido. Progress in Pattern Recognition, Image Analysis, Computer Vision, and Applications. Proceedings 19th Iberoamerican Congress, CIARP 2014, Puerto Vallarta, Mexico, November 2-5, 2014. Lecture Notes in Computer Science Volume 8827, 2014, pp 383-390.
• “A Hardware Architecture for Filtering Irreducible Testors”, Vladimir Rodríguez, José F. Martínez, Jesús A. Carrasco, Manuel S. Lazo, René Cumplido and Claudia Feregrino Uribe. Proceedings of the 2014 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2014. Dec 8-10, 2014. IEEE Catalog Number CFP14389-CDR, ISBN 978-1-4799-5943-3.
• “FSM Merging and Reduction for IP Cores Watermarking using Genetic Algorithms”, Jorge Echavarria, Alicia Morales-Reyes, Rene Cumplido and Miguel A. Salido. Proceedings of the 2014 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2014. Dec 8-10, 2014. IEEE Catalog Number CFP14389-CDR, ISBN 978-1-4799-5943-3.

2013

• “Multi-character cost-effective and high throughput architecture for content scanning”, José M. Bande, José Hernández Palancar, René Cumplido. Microprocessors and Microsystems, 37 (2013) pp. 1200–1207 ISSN 0141-9331, http://dx.doi.org/10.1016/j.micpro.2013.08.001.
• "On an external memory scheme for processor arrays", Roberto Perez-Andrade, Cesar Torres-Huitzil, Rene Cumplido, Juan M. Campos. ELEX Electronics Express. Vol. 10 (2013) No. 14 pp. 20130324. DOI: 10.1587/elex.10.20130324.
• "FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256", I. Algredo-Badillo, C. Feregrino-Uribe, R. Cumplido, M. Morales-Sandoval. Microprocessors and Microsystems. Volume 37, Issues 6-7, August-October 2013, Pages 750-757, ISSN 0141-9331, DOI: 10.1016/j.micpro.2012.06.007.
• "Collusion-Resistant Audio Fingerprinting System in the Modulated Complex Lapped Transform Domain", Jose Juan Garcia-Hernandez, Claudia Feregrino-Uribe, Rene Cumplido. Accepted for publication in PLOS ONE. June 2013, Vol.8, Issue 6, e65985. doi:10.1371/journal.pone.0065985.
• "Karatsuba-Ofman Multiplier with Integrated Modular Reduction for GF(2m)," Cuevas-Farfan, E., Morales-Sandoval, M., Morales-Reyes, A., Feregrino-Uribe, C., Algredo-Badillo, I., Kitsos, P., Cumplido, R., Advances in Electrical and Computer Engineering, vol. 13, no. 2, pp. 3-10, 2013, doi:10.4316/AECE.2013.02001.
• "Area/performance trade-off analysis of an FPGA digit-serial GF(2^m) Montgomery Multiplier based on LFSR", M. Morales-Sandoval, C. Feregrino-Uribe, P. Kitsos, R. Cumplido. Computers & Electrical Engineering. Volume 39, Issue 2, February 2013, Pages 542-549, ISSN 0045-7906, 10.1016/j.compeleceng.2012.08.010.
• "High payload data-hiding in audio signals based on a modified OFDM approach", J. J. Garcia- Hernandez, R. Parra-Michel, C. Feregrino-Uribe, and R. Cumplido. Expert systems with applications. Volume 40, Issue 8, 15 June 2013, Pages 3055-3064, ISSN 0957-4174, 10.1016/j.eswa.2012.12.021.
• “High Throughput Signature Based Platform for Network Intrusion Detection”, José Manuel Bande Serrano, José Hernández Palancar, René Cumplido. Progress in Pattern Recognition, Image Analysis, Computer Vision, and Applications. Proceedings 18th Iberoamerican Congress, CIARP 2013, November 20-13, 2013, Part I. Lecture Notes in Computer Science, Vol. 8258. pp 544-551.
• "A programmable FPGA-based cryptoprocessor for bilinear pairings over F2m," Cuevas-Farfan, E.; Morales-Sandoval, M.; Cumplido, R.; Feregrino-Uribe, C.; Algredo-Badillo, I. Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013 8th International Workshop on , vol., no., pp.1,8, 10-12 July 2013 doi: 10.1109/ReCoSoC.2013.6581528
• "A parallelization methodology for reconfigurable systems applied to edge detection," Campos, J.M.; Cumplido, R.; Feregrino-Uribe, C.; Perez-Andrade, R. Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013 8th International Workshop on , vol., no., pp.1,7, 10-12 July 2013, doi: 10.1109/ReCoSoC.2013.6581546
• “Video Error Concealment based on Data Hiding for the Emerging Video Technologies”, Francisco Aguirre-Ramos, Claudia Feregrino-Uribe, René Cumplido. 6th Pacific-Rim Symposium, PSIVT 2013, Guanajuato, Mexico, October 28-November 1, 2013, Lecture Notes in Computer Science, Vol. 8333.
• “Processor Arrays Generation for Matrix Algorithms Used in Embedded Platforms”, Roberto Perez-Andrade, Cesar Torres-Huitzil, Rene Cumplido, Juan M. Campos. Proceedings of the 2013 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013. Dic 9-11, 2013. IEEE Catalog Number: CFP13389-CDR. ISBN: 978-1-4799-2078-5.
  

2012

• "Design of processor array based on an optimized multi-projection approach", Juan M. Campos, Rene Cumplido. Advances in Electrical and Computer Engineering, vol. 12, no. 4, pp. 87-92, 2012, doi:10.4316/AECE.2012.04014.
• "A multi-cycle fixed point square root module for FPGAs", Fernando Martin del Campo, Alicia Morales- Reyes, Roberto Perez-Andrade, Rene Cumplido, A.G. Orozco-Lugo, and Claudia Feregrino. IEICE Electronics Express, Vol. 9, No. 11, pp. 971-977. DOI: 10.1587/elex.9.971.
• "Hardware-software platform for computing irreducible testors", Alejandro Rojas, Rene Cumplido, J. Ariel Carrasco-Ochoa, Claudia Feregrino, J. Francisco Martinez-Trinidad. Expert Systems with Applications, Volume 39, Issue 2, 1 February 2012, Pp 2203-2210. DOI. 10.1016/j.eswa.2011.07.004.
• "Watermarking using similarities based on fractal codification", Pedro Aaron Hernandez-Avalos, Claudia Feregrino-Uribe, Rene Cumplido. Digital Signal Processing. Volume 22, Issue 2, March 2012, Pp 324- 336. DOI/10.1016/j.dsp.2011.10.012.
• “Throughput and Efficiency Analysis of Unrolled Hardware Architectures for the SHA-512 Hash Algorithm”, Algredo-Badillo, I.; Morales-Sandoval, M.; Feregrino-Uribe, C.; Cumplido, R., 2012 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp.63-68, 19-21 Aug. 2012, doi: 10.1109/ISVLSI.2012.63.

2011

• "On the Implementation of a Hardware Architecture for an Audio Data Hiding System Signal Processing," Jose Juan Garcia-Hernandez, Claudia Feregrino-Uribe, Rene Cumplido, Carolina Reta. Journal of Signal Processing Systems - Springer Verlag. Vol. 64, No.3, pp- 457-468. DOI: 10.1007/s11265-010-0503- 8.
• “On Model-Driven Engineering of Reconfigurable Digital Control Hardware Systems,” Tomás Balderas, Gustavo Rodriguez and René Cumplido. Included in the book “Reconfigurable Embedded Control Systems:Applications for Flexibility and Agility”. Edited by: Mohamed Khalgui, Hans-Michael Hanisch, DOI: 10.4018/978-1-60960-086-0, ISBN13: 9781609600860. IGI Global. USA 2011.
• “On an Hybrid and General Control Scheme for Algorithms Represented as a Polytope”, Roberto Pérez-Andrade, César Torres-Huitzil, René Cumplido, Juan M. Campos. RAW Workshop 2011, 2011 IEEE International Parallel & Distributed Processing Symposium. May 2011. Pp. 325-328. ISBN: 1530-2075/11, DOI 10.1109/IPDPS.2011.163. IEEE Catalog Number: CFP1121B-PRT.
• “A Reconfigurable GF(2M) Elliptic Curve Cryptographic Coprocessor”, M. Morales-Sandoval, C. Feregrino-Uribe, R. Cumplido, I. Algredo-Badillo. 2011 VII Southern Conference on Programmable Logic (SPL). IEEE Press. Pp.209-214. ISBN: 978-1-4244-8846-9. April 2011.
• “Invited paper: Implementing digital data hiding algorithms in reconfigurable hardware — Experiences on teaching and research”, Cumplido, R.; Feregrino-Uribe, C.; Garcia-Hernandez, J.J. 2011 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Issue Date: 20-22 June 2011, On page(s): 1 – 6, DOI. Digital Object Identifier: 10.1109/ReCoSoC.2011.5981526. IEEE Press.

2010

• “A Versatile Hardware Architecture for a Constant False Alarm Rate Processor Based on a Linear Insertion Sorter,” Roberto Perez-Andrade, René Cumplido, Claudia Feregrino-Uribe, Fernando Martin Del Campo. Digital Signal Processing, Volume 20, Issue 6, December 2010, Pages 1733-1747. ISSN 1051-2004, DOI: 10.1016/j.dsp.2010.02.001.
• “Improving the security of Fallahpour's audio  watermarking scheme,” Jose Juan Garcia-Hernandez, Claudia Feregrino-Uribe, Rene Cumplido and Ramon Parra-Michel. IEICE Electronics Express, Vol. 7 (2010) , No. 14. ISSN: 1349-2543. DOI: 10.1587/elex.7.628.
• "On the Design of a Hardware-Software Architecture for acceleration of SVM´s training”, Lazaro Bustio-Martinez, René Cumplido, Claudia Feregrino-Uribe and José Hernández-Palancar. 2nd Mexican Conference on Pattern Recognition, MCPR 2010. LNCS Springer Verlag. Sept 2010.
• "A Highly Parallel Algorithm for Frequent Itemset Mining”, Alejandro Mesa, Claudia Feregrino-Uribe, René Cumplido and José Hernández-Palancar. 2nd Mexican Conference on Pattern Recognition, MCPR 2010. LNCS Springer Verlag. Sept 2010.
• "Towards the Construction of a Benchmark for Video Watermarking Systems: Temporal Desynchronization Attacks", Pedro A. Hernandez-Avalos, Claudia Feregrino-Uribe, Rene Cumplido and Jose Juan Garcia-Hernandez. 53rd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS '10.
• "A UML 2.0 Profile to Model Block Cipher Algorithms", Tomas Balderas-Contreras, Gustavo Rodriguez and Rene Cumplido. 6th European Conference on Modelling Foundations and Applications, ECMFA 2010. LNCS, Vol. 6138, pp.20-31, DOI: 10.1007/978-3-642-13595-8, Springer Verlag, June 2010.
• "Towards a Reconfigurable Platform to Implement Security Architectures of wireless Communications Standards Based on the AES-CCM Algorithm”, Ignacio Algredo-Badillo, Claudia Feregrino-Uribe, René Cumplido, Miguel Morales-Sandoval. Book chapter included in “New Trends in Electrical Engineering, Automatic Control, Computing and Communication Sciences”, Edited by Carlos A. Coello, Alex Poznyak, José Moreno and Vadim Azhmyakov. Logos Verlag, Berlin, Germany. ISBN 978-3-8325-2429-6. 2010.
• “Hardware Architecture for Adaptive Filtering based on Energy-CFAR processor for Radar Target Detection”, Santos Lopez-Estrada, Rene Cumplido. IEICE Electronics Express, Vol. 7 , No. 9, pp.628-633. May 2010.
• “Efficient hardware architecture for the AES-CCM protocol of the IEEE 802.11i standard”, Ignacio Algredo-Badillo, Claudia Feregrino-Uribe, René Cumplido, Miguel Morales-Sandoval. Computers & Electrical Engineering, Vol. 36, Issue 3, May 2010, Pp. 565-577. DOI:10.1016/j.compeleceng.2009.12.011.
• “A single formula and its implementation in FPGA for elliptic curve point addition using affine representation”,  Miguel Morales-Sandoval, Claudia Feregrino-Uribe, René Cumplido, Ignacio Algredo-Badillo. Journal of Circuits, Systems and Computers (JCSC), Vol. 19, Issue 2, April 2010, pp. 425-433 DOI: 10.1142/S0218126610006153.
• “Towards a reconfigurable hardware architecture for implementing a LDPC module suitable for software radio systems”, Rene Cumplido, Juan Campos, Claudia Feregrino-Uribe, Roberto Perez. Dagstuhl Seminar Proceedings 10281, Dynamically Reconfigurable Architectures, Edited by P. M. Athanas, J. Becker, J. Teich, I. Verbauwhede,ISSN  1862 - 4405. July 2010.

2009

• "A Versatile Linear Insertion Sorter Based on a FIFO Scheme", Jose Roberto Perez Andrade, Rene Cumplido, Fernando Martin del Campo, Claudia Feregrino Uribe. Elsevier Microelectronics Journal, Vol 40, No. 12, Dec. 2009, pp. 1705-1713, DOI: 10.1016/j.mejo.2009.08.006. ISSN: 0026-2692.
• "Video watermarking scheme resistant to MPEG compression", Hernandez-Avalos, P.A.; Feregrino-Uribe, C.; Cumplido, R.; Garcia-Hernandez, J.J. 52nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS '09, pp: 853-858, Digital Object Identifier 10.1109/MWSCAS.2009.523590. IEEE Press. Aug. 2009.
• "A Knowledge-based System for Sea State Recognition and Target Detection using a Single Marine Radar Sensor", S. López-Estrada and R. Cumplido. IASTED Computational Intelligence conference (CI 2009), Acta Press, ISBN : 978-0-88986-806-9, pp. 30-36. Aug 2009.
• "A System on a Programmable Chip Architecture for Data-Dependent Superimposed Training Channel Estimation", Fernando Martin del Campo, Rene Cumplido, Roberto Perez-Andrade, and A. G. Orozco- Lugo. International Journal of Reconfigurable Computing, Volume 2009 (2009), Article ID 912301, doi:10.1155/2009/912301.
• "FPGA-architecture for Knowledge-Based Target Detection in Radar signal Processing", Santos Lopez Estrada, Rene Cumplido. Enginnering of Reconfigurable Systems and Algorithms, ERSA 09, CSREA Press, ISBN:1-60132-101-5, July 2009.
• "Efficient implementation of the RDM-QIM algorithm in an FPGA", Jose Juan Garcia-Hernandez, Carolina Reta, Rene Cumplido and Claudia Feregrino-Uribe. IEICE Electronics Express, Vol. 6, No. 14, pp.1064- 1070. May 2009.
• "An Area/Performance Trade-Off Analysis of a GF(2m) Multiplier Architecture for Elliptic Curve Cryptography", Miguel Morales-Sandoval, Claudia Feregrino-Uribe, Rene Cumplido, Ignacio Algredo- Badillo. Computers and Electrical Engineering. Computers & Electrical Engineering, Elsevier, Vol. 35, No. 1, January 2009, Pp. 54-58, 2009, ISSN:0045-7906.
• “Watermarking Based on Iterated Function Systems”, Pedro A. Hernández Avalos, Claudia Feregrino Uribe, Roger Luis Velázquez, René A. Cumplido Parra. 2009 Mexican International Conference on Computer Science (ENC), Sept. 2009, pp. 339 – 344, Print ISBN: 978-1-4244-5258-3, DOI: 10.1109/ENC.2009.58.
• “A Run Time Reconfigurable Co-Processor for Elliptic Curve Scalar Multiplication”, Miguel Morales-Sandoval, Claudia Feregrino-Uribe, Rene Cumplido and Ignacio Algredo-Badillo. 2009 Mexican International Conference on Computer Science (ENC), Sept. 2009, pp. 345 – 350, Print ISBN: 978-1-4244-5258-3, DOI: 10.1109/ENC.2009.57.

2008

• “Hybrid Architecture for Data-Dependent Superimposed Training in Digital Receivers,”Fernando Martín del Campo, René Cumplido, Roberto Perez-Andrade, and A.G. Orozco-Lugo. 2008 International Conference on ReConFigurable Computing and FPGAs, ReConFig08, Dic. 2008. IEEE Computer Society Press. ISBN 978-0-7695-3437-9.
• “FPGA Implementation of a Modulated Complex Lapped Transform for Watermarking Systems,” Jose Juan Garcia-Hernandez, Claudia Feregrino-Uribe, and Rene Cumplido. 2008 International Conference on ReConFigurable Computing and FPGAs, ReConFig08, Dic. 2008. IEEE Computer Society Press. ISBN 978-0-7695-3437-9.
• “FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks,” Ignacio Algredo-Badillo, Claudia Feregrino-Uribe, René Cumplido, and Miguel Morales-Sandoval. 2008 International Conference on ReConFigurable Computing and FPGAs, ReConFig08, Dic. 2008. IEEE Computer Society Press. ISBN 978-0-7695-3437-9.
• “A Reversible Data Hiding Algorithm for Radiological Medical Images and Its Hardware Implementation,” Z. Jezabel Guzmán Zavaleta, Claudia Feregrino Uribe, and René Cumplido. 2008 International Conference on ReConFigurable Computing and FPGAs, ReConFig08, Dic. 2008. IEEE Computer Society Press. ISBN 978-0-7695-3437-9.
• “On the design and implementation of a RISC processor extension for the KASUMI encryption algorithm,” Tomas Balderas-Contreras, Rene Cumplido, Claudia Feregrino-Uribe. Computers & Electrical Engineering, Vol. 34, Issue 6, pp. 531-546, Nov 2008.
• “FPGA Implementation Cost and Performance Evaluation of the IEEE 802.16e and IEEE 802.11i Security Architectures Based on AES-CCM,” Ignacio Algredo-Badillo, Claudia Feregrino-Uribe, René Cumplido, Miguel Morales-Sandoval. 5th International Conference on Electrical Engineering, Computing Science and Automatic Control, CCE 2008, November 2008. IEEE Press. ISBN 978-1-4244-2499-3.
• “A Reversible Data Hiding Algorithm for Radiological Medical Images,” Z. Jezabel Guzmán Zavaleta, Claudia Feregrino Uribe, José Alberto Martínez Villanueva, René Cumplido. 5th International Conference on Electrical Engineering, Computing Science and Automatic Control, CCE 2008, November 2008. IEEE Press. ISBN 978-1-4244-2499-3.
• “Design and Implementation of a Non-Pipelined MD5 Hardware Architecture”, Ignacio Algredo Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval. IEICE Transactions on Information and Systems Vol. E91-D, No.10, pp.2519-2523, Oct 2008.
• "A Versatile Hardware Architecture for a CFAR Detector Based on a Linear Insertion Sorter”, Roberto Perez-Andrade, Rene Cumplido, Claudia Feregrino-Uribe, Fernando Martin Del Campo. 18th International Conference on Field Programmable Logic and Applications, FPL08, Sept. 2008. IEEE Press. ISBN: 978-1-4244-1961-6.
• “A SOPC Architecture for Data-dependent Superimposed Training Channel Estimation”, Fernando Martín del Campo, René Cumplido, Roberto Pérez-Andrade, A.G. Orozco-Lugo. 4th International Workshop on Reconfigurable Communication Centric System-on-Chips, ReCoSoc´08, June 2008. ISBN: 978-84-691-3603-4.
• “A Versatile Linear Insertion Sorter Based on a FIFO Scheme”, Roberto Perez-Andrade, Rene Cumplido, Fernando Martin Del Campo, Claudia Feregrino-Uribe. IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2008. IEEE Computer Society, ISBN 978-0-7695-3170-0.
• "FPGA Hardware Architecture of the Steganographic Context Technique", Edgar Gómez Hernández, Claudia Feregino, René Cumplido. 18th International Conference on Electronics, Communications and Computers, CONIELECOMP 2008. IEEE Computer Society.
• "Comparación de la Eficiencia en Hardware de los Cifradores de Flujo Grain, Mickey-128 y Trivium de Ecrypt", Blanca Nydia Pérez Camacho, Rene Cumplido Parra. XIV Iberchip Workshop 2008, Puebla, México ISBN. 13-978-968-7938-03-5
• "Arquitectura FPGA Parametrizable para Convolución de Imágenes" J.C. Moctezuma Eugenio, M. Arias Estrada, R.Cumplido Parra. XIV Iberchip Workshop 2008, Puebla, México ISBN. 13-978-968-7938-03-5

2007

• “FPGA-Based Architecture for Computing Testors”, Alejandro Rojas, René Cumplido, J. Ariel Carrasco-Ochoa, Claudia Feregrino, and J. Francisco Martínez-Trinidad, H. Yin et al. (Eds.): 8th International Conference on Intelligent Data Engineering and Automated Learning (IDEAL'07), LNCS 4881, pp. 188–197, Springer-Verlag, 2007.

2006

• "Parallel Hardware/Software Architecture for the BWT and LZ77 Lossless Data Compression Algorithms", Virgilio Zúñiga, Claudia Feregrino, René Cumplido. Journal of Computing and Systems, Vol. 10 No. 2, 2006, pp 172-188. ISSN 1405-5546. IPN, Mexico, Nov 2006.
• "On the Design and Implementation of a High Performance Configurable Architecture for Testor Identification", René Cumplido, Ariel Carrasco, Claudia Feregrino. CIARP06, Lecture Notes in Computer Science, Vol. 4225, Springer Verlag, November 2006, ISBN 3-540-46556-1, p. 665-673.
• "Design and Implementation of an FPGA-based 1.452-Gbps Non-pipelined AES", Ignacio Algredo-Badillo, Claudia Feregrino-Uribe, René Cumplido. ICCSA06. Lecture Notes on Computer Science, Springer Verlag, Vol. 3982, p. 456-465, May 2006. ISBN 3-540-34075-0.
• "Decision Tree Based FPGA-Architecture for Texture Sea State Classification", Santos Martin López Estrada and René Cumplido, 2006 IEEE International Conference on Reconfigurable Computing and FPGAs, ReConFig06, ISBN 1-4244-0689-7, p. 191-197, September 2006.
• "Pipelined FPGA-based CORDIC Architecture for a Digital Sine and Cosine Waves Generator", Esteban O. Garcia, René Cumplido, Miguel Arias, 3rd International Conference on Electrical and Electronics Engineering, ICEEE06, Sept. 2006. IEEE Press. ISBN 1-4244-0403-7. p. 104-107.
• "A Runtime Reconfigurable Architecture for Viterbi Decoding", Juan Manuel Campos, René Cumplido, 3rd International Conference on Electrical and Electronics Engineering, ICEEE06, Sept. 2006. IEEE Press. ISBN 1-4244-0403-7. p. 382-385.

2005

• "On the design of an FPGA-Based OFDM modulator for IEEE 802.11a", Joaquin Garcia, Rene Cumplido, 2nd International Conference on Electrical and Electronics Engineering, ICEEE05, September 2005. IEEE Press. ISBN 0-7803-9231-0.
• "An FPGA Parallel Sorting Architecture for the Burrows Wheeler Transform", José Martínez, René Cumplido, Claudia Feregrino. 2005 International Conference on Reconfigurable Computing and FPGAs, September 2005. IEEE CS Press. ISBN 0-7695-2456-7.
• "On the design of an FPGA-Based OFDM modulator for IEEE 802.16-2004", Joaquin Garcia, Rene Cumplido. 2005 International Conference on Reconfigurable Computing and FPGAs, September 2005. IEEE Computer Society Press. ISBN 0-7695-2456-7.
• "Fusion center with neural network for target detection in background clutter", Santos López-Estrada, René Cumplido. Sixth Mexican International Conference in Computer Science, ENC05, September 2005, IEEE Computer Society Press. ISBN 0-7695-2454-0.
• "High Performance Encryption Cores for 3G Networks", Tomás Balderas-Contreras, René Cumplido. Proceedings of the 42nd annual ACM IEEE Conference on Design Automation 2005, DAC05,June 2005. ISBN:1-59593-058-2.
• "A High Performance Processor for embedded Real-Time Control", René Cumplido, Simon Jones, Roger Goodall y Stephen Bateman. IEEE Transactions on Control Systems Technology, Vol. 13, No. 3, pp. 485-492, May 2005.

2004

• “Design and Implementation of a CFAR Processor for Target Detection”, César Torres-Huitzil, Rene Cumplido-Parra, Santos López-Estrada, 14th International Conference on Field Programmable Logic, FPL04, August 2004. Lectures Notes on Cumputer Science Vol. 3203, pp. 943-947. ISBN 3540229892.
• “An Efficient FPGA Architecture for Block Ciphering in Third Generation Cellular Network” Tomás Balderas Contreras, René A. Cumplido Parra. Research on Computer Science Vol 10. Advances in: Artificial Intelligence, Computing Science and Computer engineering, IPN, Mexico. ISBN:970-36-0194-4.
• “An Efficient FPGA Architecture for Block Ciphering in Third Generation Cellular Network” Tomás Balderas Contreras, René A. Cumplido Parra. International Congress on Computing, CIC04. México. October 2004. ISBN: 970-36-0194-4.
• “Diseño y Desarrollo de una Plataforma Criptográfica Reconfigurable del Alto Desempeño” Ignacio Algredo Badillo, René Cumplido Parra y Claudia Feregrino. International Congress on Computing, CIC04. México. October 2004. ISBN: 970-36-0194-4.
• “DETECTA: Una Herramienta Software para Evaluar Esquemas de Detección de Blancos en Presencia de Ruido Marítimo”, Santos López Estrada, René Cumplido Parra. International Congress on Computing, CIC04. México. October 2004. ISBN: 970-36-0194-4.
• “An Efficient Hardware Implementation of the KASUMI Block Cipher for Third Generation Cellular Networks”, Tomás Balderas Contreras, René A. Cumplido Parra. Global signal Processing Conference, GSPx 2004. Santa Clara CA. September 2004.
• “A Configurable FPGA-based Hardware Architecture for Adaptive Processing of Noisy Signals for Target Detection Based on Constant False Alarm Rate (CFAR) Algorithms”, Rene Cumplido, Cesar Torres, Santos Lopez. Global signal Processing Conference, GSPx 2004. Santa Clara CA. September 2004.
• “A Hybrid Approach for Target Detection Using CFAR Algorithm and Image Processing”, Santos López-Estrada, Rene Cumplido-Parra, Cesar Torres-Huitzil. Fifth Mexican International Conference in Computer Science, ENC'04, September 2004, IEEE Computer Society Press, ISBN: 0-7695-2160-6/04. pp. 108-115.
• “FPGA Based Architecture for Radar’s STC, FTC and Gain Modules”, Joaquín García, Gilberto Viveros, René Cumplido. 2004 International Conference on Reconfigurable Computing and FPGAs, Colima, México, September 2004. ISBN 970-692-169-9.
• “On the Implementation of an efficient FPGA-based CFAR Processor for Target Detection”, Rene Cumplido, César Torres, Santos López. 1st International Conference on electrical and Electronics Engineering, September 2004. IEEE Catalog number: 04EX865C, ISBN: 0-7803-8532-2.
• “An Efficient Reuse-Based Approach to Implement the 3GPP KASUMI Block Cipher”, Tomás Balderas-Contreras, René A. Cumplido-Parra. 1st International Conference on electrical and Electronics Engineering, September 2004. IEEE Catalog number: 04EX865C, ISBN: 0-7803-8532-2.

1998-2003

• “Compresión Run Lenght con FPGA aplicada a imágenes de información geográfica en formatos raster y vector”, Santos Martín López Estrada, René A. Cumplido Parra, Claudia Feregrino Uribe. Taller de Cómputo Reconfigurable y FPGAs, ENC03, Apizaco, México, September 2003.
• “Implementación FPGA del cálculo de profundidades en la recuperación de 3D usando luz estructurada”, Díaz Hernández Carlos Alberto, López Gutiérrez Luis David, Arias Estrada Miguel O., Feregrino Uribe Claudia y Cumplido Parra Rene A. Taller de Cómputo Reconfigurable y FPGAs, ENC03, Apizaco, México, September 2003.
• “Convolucionador SIMD acoplado a HALCÓN”, Liz N. Castillo Jiménez, Gerardo Sosa Ramírez y René A. Cumplido Parra. Taller de Cómputo Reconfigurable y FPGAs, ENC03, Apizaco, México, September 2003.
• "High Performance Control System Processor”, Rene A. Cumplido-Parra, Simon R. Jones, Roger M. Goodall, Fiona Mitchell y Stephen Bateman, Capítulo publicado en el libro "System Design Automation: Fundamentals, Principles, Methods, Examples", Edited by Renate Merker and Wolfgang Schwarz, Kluwer Academic Publishers, ISBN 0-7923-7313-8, páginas 140-151, March 2001.
• "A Control System Processor Architecture For Complex LTI Controllers", R. Goodall, S. Jones, R.A. Cumplido-Parra, F. Mitchell, S. Bateman, , Proceedings, 6th IFAC Workshop on Algorithms and Architectures for Real-Time Control, (AARTC 2000), Palma de Mallorca, Spain, May 2000.
• "High Performance Control System Processor", Rene A. Cumplido-Parra, Simon R. Jones, Roger M. Goodall, Fiona Mitchell y Stephen Bateman, , Proceedings of the 3rd Workshop on System Design Automation - SDA 2000, Dresden, Germany, March 2000.
• "Digital Filtering for High Performance Real-Time Control," Roger Goodall, Simon Jones y Rene Cumplido-Parra, IEE Colloquium on Digital Filters: An enabling technology, London, April 1998.

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