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Journal Publications

2016

2015

2014

2013

2012

2011

2010

2009

2008

2006

2001

International Conferences / Memorias en extenso con arbitraje internacional

 

2016

 

2015

 

2014

 

 

 

2013

 

41. Aguirre-Ramos, F., Feregrino-Uribe, C., Cumplido, R.: Video Error Concealment Based on Data Hiding for the Emerging Video Technologies. In: Klette, R., Rivera, M., Satoh, S. (eds.) PSIVT 2013. LNCS, vol. 8333, pp. 454-467.

42. Cuevas-Farfan, E.; Morales-Sandoval, M.; Cumplido, R.; Feregrino-Uribe, C.; Algredo-Badillo, I., "A programmable FPGA-based cryptoprocessor for bilinear pairings over F2m", Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013 8th International Workshop on , vol., no., pp.1,8, 10-12 July 2013 doi: 10.1109/ReCoSoC.2013.6581528

43. Campos, J.M.; Cumplido, R.; Feregrino-Uribe, C.; Perez-Andrade, R., "A parallelization methodology for reconfigurable systems applied to edge detection," Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013 8th International Workshop on , vol., no., pp.1,7, 10-12 July 2013, doi: 10.1109/ReCoSoC.2013.6581546.

2012

 

44. Algredo-Badillo, I.; Morales-Sandoval, M.; Feregrino-Uribe, C.; Cumplido, R., Throughput and Efficiency Analysis of Unrolled Hardware Architectures for the SHA-512 Hash Algorithm, 2012 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp.63-68, 19-21 Aug. 2012, doi: 10.1109/ISVLSI.2012.63.

 

2011

 

45. M. Morales-Sandoval, C. Feregrino-Uribe, R. Cumplido, I. Algredo-Badillo, A Reconfigurable GF(2M) Elliptic Curve Cryptographic Coprocessor, 2011 VII Southern Conference on Programmable Logic (SPL). IEEE Xplore. Pp.209-214. ISBN: 978-1-4244-8846-9. April 2011.

46. Cumplido, R.; Feregrino-Uribe, C.; Garcia-Hernandez, J.J. , Invited paper: Implementing digital data hiding algorithms in reconfigurable hardware - Experiences on teaching and research, 2011 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Issue Date: 20-22 June 2011, On page(s): 1 - 6, DOI. Digital Object Identifier: 10.1109/ReCoSoC.2011.5981526. IEEE Xplore.

 

2010

 

47. Lázaro Bustio-Martínez, René Cumplido, José Hernández-Palancar and Claudia Feregrino-Uribe, On the Design of a Hardware-Software Architecture for Acceleration of SVM's Training Phase, ADVANCES IN PATTERN RECOGNITION, Lecture Notes in Computer Science, 2010, Volume 6256/2010, 281-290, DOI: 10.1007/978-3-642-15992-3_30

48. Alejandro Mesa, Claudia Feregrino-Uribe, René Cumplido and José Hernández-Palancar, A Highly Parallel Algorithm for Frequent Itemset Mining, ADVANCES IN PATTERN RECOGNITION, Lecture Notes in Computer Science, 2010, Volume 6256/2010, 291-300, DOI: 10.1007/978-3-642-15992-3_30.

49. Rene Cumplido, Juan Campos, Claudia Feregrino-Uribe, Roberto Perez, Towards a recongurable hardware architecture for implementing a LDPC module suitable for software radio systems, Dagstuhl Seminar Proceedings 10281 Dynamically Reconfigurable Architectures, Edited by P. M. Athanas, J. Becker, J. Teich, I. Verbauwhede, ISSN: 1862 - 4405. July 2010.

50. Pedro A. Hernandez-Avalos, Claudia Feregrino-Uribe, Rene Cumplido and Jose Juan Garcia-Hernandez, Towards the Construction of a Benchmark for Video Watermarking Systems: Temporal Desynchronization Attacks, Proceedings of the 53nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2010, pp. 628-631, ISBN: 978-1-4244-7772-2, Seattle, WA, 2010.

 

2009

 

51. Pedro Aarón Hernández-Avalos, Claudia Feregrino-Uribe, René Cumplido, José Juan García-Hernández, Video Watermarking Scheme resistant to MPEG Compression, Proceedings of the 52nd IEEE International Midwest Symposium on Circuits and Systems, 2009. Pp. 853 - 858. Cancun, Mexico, 2009.

52. Héctor Borrayo-Sandoval, Ramón Parra Michel, Luis F. González-Pérez, Fernando Landeros Printzen, Claudia Feregrino-Uribe, Design and Implementation of a Configurable Interleaver/Deinterleaver for Turbo Codes in 3GPP Standard, IEEE Proceedings of the International Conference on Reconfigurable Computing and FPGAs, Cancún México, Dec. 2009. Pp. 320-325.

53. Miguel Morales-Sandoval, Claudia Feregrino-Uribe, René Cumplido, Ignacio Algredo-Badillo, A Run Time Reconfigurable Co-processor for Elliptic Curve Scalar Multiplication, IEEE Proceedings of the 2009 Mexican International Conference on Computer Science, 2009, pp.345-350, ISBN: 978-0-7695-3882-2

54. Pedro A. Hernández Ávalos, Claudia Feregrino Uribe, Roger Luis Velázquez, René A. Cumplido Parra, Watermarking Based on Iterated Function Systems, IEEE Proceedings of the 2009 Mexican International Conference on Computer Science, 2009, pp.339-344, ISBN: 978-0-7695-3882-2.

2008

55. Perez-Andrade, R.; Cumplido, R.; Feregrino-Uribe, C.; Del Campo, F.M., A Versatile Hardware Architecture for a CFAR Detector based on a Linear Insertion Sorter, IEEE Proceedings of the International Conference on Field Programmable Logic and Applications, FPL, 2008. Germany, Sept. 8-10, Pp. 467-470.

56. Z. Jezabel Guzman Zavaleta, Claudia Feregrino and Rene Cumplido, A Reversible Data Hiding Algorithm for Radiological Medical Images and its Hardware Implementation, 2008 International Conference on ReConFigurable Computing and FPGAs, ReConFig08, Cancún, México, Dic. 2008. IEEE Computer Society Press. ISBN 978-0-7695-3437-9.

57. Z. Jezabel Guzmán Zavaleta, Claudia Feregrino-Uribe, José Alberto Martínez Villanueva, René Cumplido, A Reversible Data Hiding Algorithm for Radiological Medical Images, IEEE Proceedings of the 5th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE 2008), México, D.F., Pp. 280-285. ISBN: 978-1-4244-2499-3.

58. Ignacio Algredo-Badillo, Claudia Feregrino-Uribe, René Cumplido, and Miguel Morales-Sandoval, FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks, 2008 International Conference on ReConFigurable Computing and FPGAs, ReConFig08, Cancún, México, Dic. 2008. IEEE Computer Society Press. ISBN 978-0-7695-3437-9.

59. Ignacio Algredo-Badillo, Claudia Feregrino-Uribe, René Cumplido, Miguel Morales-Sandoval, FPGA Implementation Cost and Performance Evaluation of the IEEE 802.16e and IEEE 802.11i Security Architectures Based on AES-CCM, IEEE Proceedings of the 5th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE 2008), México, D.F., Pp. 304-309. ISBN: 978-1-4244-2499-3.

60. Jose Juan Garcia-Hernandez, Claudia Feregrino-Uribe, and Rene Cumplido, FPGA Implementation of a Modulated Complex Lapped Transform for Watermarking Systems, 2008 International Conference on ReConFigurable Computing and FPGAs, ReConFig08, Cancún, México, Dic. 2008. IEEE Computer Society Press. ISBN 978-0-7695-3437-9.

61. José Alberto Martínez Villanueva, Claudia Feregrino Uribe, Z. Jezabel Guzmán Zavaleta, Watermarking Algorithms Analysis on Radiological Images, IEEE Proceedings of the 5th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE 2008), México, D.F., Pp. 298-303. ISBN: 978-1-4244-2499-3.

62. Raudel Hernández León, Airel Pérez Suárez, Claudia Feregrino Uribe, Zobeida Jezabel Guzmán Zavaleta, An Algorithm for Mining Frequent Itemsets, IEEE Proceedings of the 5th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE 2008), México, D.F., Pp. 334-339. ISBN: 978-1-4244-2499-3.

63. Roberto Perez-Andrade , Rene Cumplido , Fernando Martin Del Campo , Claudia Feregrino-Uribe, A Versatile Linear Insertion Sorter Based on a FIFO Scheme, IEEE Computer Society Annual Symposium on VLSI, pp. 357-362, April 2008.

64. Edgar Gómez-Hernández, Claudia Feregrino-Uribe, Rene Cumplido, FPGA Hardware Architecture of the Steganographic ConText Technique, IEEE Proceedings of th 18th International Conference on Electronics, Communications and Computers, CONIELECOMP.2008, págs. 123-128.

65. Ariel Molina-Rueda, Fernando Uceda-Ponga, Claudia Feregrino Uribe, Extended Period LFSR using Variable TAP Function, Proceedings of th 18th International Conference on Electronics, Communications and Computers, CONIELECOMP.2008, págs. 129-132.

2007

66. Alejandro Rojas, René Cumplido, J. Ariel Carrasco-Ochoa, Claudia Feregrino, J. Francisco Martínez-Trinidad, FPGA-based Implementation of the BT Algorithm for Computing Testors, IDEAL Conference 2007, Lecture Notes in Computer Science vol. 4881, págs. 188-197.

67. Dulce R. Herrera-Moro, Raúl Rodríguez Colín , Claudia Feregrino-Uribe, Adaptive Steganography based on textures, IEEE Proceedings 17th International Conference on Electronics, Communications and Computers CONIELECOMP 2007. pp. 34. February 2007. Doi bookmark: 10.1109/CONIELECOMP.2007.9

68. Rodríguez-Colín Raúl, Feregrino-Uribe Claudia, Trinidad-Blas Gershom de J, Data Hiding Scheme for Medical Images, IEEE Proceedings 17th International Conference on Electronics, Communications and Computers, CONIELECOMP'07, 2007, pp. 32. http://doi.ieeecomputersociety.org/10.1109/CONIELECOMP.2007.14

69. J. Alberto Méndez-Polanco, A. Cristina Palacios García, Raúl Rodríguez-Colín, Claudia Feregrino-Uribe, Digital Watermarking Based on Image Centroid Resistant to Rotation and Scaling, IEEE Proceedings 17th International Conference on Electronics, Communications and Computers CONIELECOMP 2007.

2006

 

70. Miguel Morales Sandoval, Claudia Feregrino Uribe, GF(2m) Arithmetic Modules for Elliptic Curve Cryptography, International Conference on Reconfigurable Computing and FPGAs, ReConFig 06, 20-22 Septiembre 2006, San Luis Potosí, Mexico. IEEE Proceedings. Pp. 176-183.

71. Roshan Duraisamy, Zoran Salcic, Miguel Morales Sandoval, Claudia Feregrino Uribe, A Fast Elliptic Curve Based Key Agreement Protocol-in-Chip (PoC) for securing Networked Embedded Systems, 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA) 2006, Agosto 16 - 18, Sydney Australia. Pp. 154-161.

2005

72. José Martínez, René Cumplido, Claudia Feregrino, An FPGA-based Parallel Sorting Architecture for the Burrows Wheeler Transform, International Conference on Reconfigurable Computing and FPGAs, ReConFig 05, Puebla, Mexico. IEEE Proceedings. ISBN 0-7695-2456-7.

73. Miguel Morales Sandoval, Claudia Feregrino Uribe, A Hardware Architecture for Elliptic Curve Cryptography and Lossless Data Compression, International Conference on Electronics, Communications and Computers, CONIELECOMP Conference 2005, IEEE Computer Society, ISBN 0-7695-2283-1, pp. 113-118, February 2005.

74. Carlos Avendaño Pérez, Claudia Feregrino Uribe y Gonzalo Navarro Badino, Búsqueda Aproximada Directa En Texto Comprimido, International Conference on Electronics, Communications and Computers, CONIELECOMP Conference 2005, ISBN 0-7695-2283-1, pp. 258-261, February 2005.

2004

75. Carlos Avendaño, Claudia Feregrino y Gonzalo Navarro, Mejorando un Algoritmo para Búsqueda Aproximada, XIII International Congress on Computing 2004, 13-15 Oct, México DF. ISBN: 970-36-0194-4.

76. Ignacio Algredo Badillo, René Cumplido Parra y Claudia Feregrino, "Diseño y Desarrollo de una Plataforma Criptográfica Reconfigurable de Alto Desempeño", 2004 XIII International Congress on Computing, 13-15 Oct, México DF. ISBN: 970-36-0194-4.

77. Ignacio Algredo Badillo, René Cumplido Parra y Claudia Feregrino, "Rondas Parcialmente Desenrolladas para Implementaciones a 1 Gpbs en FPGA de los Algoritmos SHA-1 y MD5", 2004 XIII International Congress on Computing, 13-15 Oct, México DF. ISBN: 970-36-0194-4.

78. Claudia Feregrino, Rodolfo González y Karen Bayardo, "Interfaz Hardware para Captura de imagenes en equipos radiológicos", Memorias en CD del Congreso IEEE Latin American CAS Tour & International Conference on Electronic Design (ICED), Veracruz, Noviembre 2004.

79. Ignacio Algredo-Badillo, René Armando Cumplido-Parra, Claudia Feregrino-Uribe, "Desarrollo de un Módulo MD5 para un Sistema Criptográfico Reconfigurable en un FPGA", Congreso Internacional de Cómputo Reconfigurable y FPGAs, Colima, México, Septiembre, 2004.

80. Ignacio Algredo-Badillo, René Armando Cumplido-Parra, Claudia Feregrino-Uribe, "Implementación de un Módulo SHA-1 para una Plataforma Reconfigurable Criptográfica en FPGA a 1 Gbps", Congreso Internacional de Cómputo Reconfigurable y FPGAs, Colima, México, Septiembre, 2004.

81. Virgilio Zúñiga-Grajeda, Claudia Feregrino-Uribe, Implementación en un FPGA del Modelo de Compresión de Datos PPMC, Congreso Internacional de Cómputo Reconfigurable y FPGAs, Colima, México, Septiembre, 2004.

82. Miguel Morales-Sandoval, Claudia Feregrino-Uribe, "On the Design and Implementation of an FPGA-Based Lossless Data Compressor", Congreso Internacional de Cómputo Reconfigurable y FPGAs, Colima, México, Septiembre, 2004.

83. Miguel Morales Sandoval y Claudia Feregrino Uribe, "On the Hardware Design of an Elliptic Curve Cryptosystem", Congreso Internacional ENC-2004, Colima, en México, del 20 al 24 de Septiembre de 2004. págs. 64-70.

2003


84. Marco Aurelio Nuño Maganda, Miguel Arias Estrada, Claudia Feregrino Uribe, Three Video Applications using an FPGA based Pyramid Implementation: Tracking, Mosaics and Stabilization, FPT 2003, International Conference on Field-Programmable Technology, Tokio, Japón, pp. 336 - 339, Diciembre, 2003.

85. Feregrino Uribe C., High-Performance PPMC Compression Algorithm, IEEE Computer Society, ISBN 0-7695-1915-6, Fourth Mexican International Conference on Computer Science, págs. 135 - 142, Apizaco, Tlax. México, Septiembre, 2003.

86. Santos Martín López Estrada, René A. Cumplido Parra, Claudia Feregrino Uribe, Compresión Run Lenght con FPGA aplicada a Imágenes de Información Geográfica en Formatos Raster y Vector, ENC 2003, IV Congreso Internacional de Ciencias de la Computación, Avances en Ciencias de la Computación, págs. 109-114, Apizaco, Tlax. México, Septiembre, 2003.

87. Carlos Alberto Díaz Hernández, Luis David López Gutiérrez, Miguel O. , Claudia Feregrino Uribe y René A. Cumplido Parra, Implementación FPGA del Cálculo de Profundidades en la Recuperación de 3D usando Luz Estructurada, ENC 2003, IV Congreso Internacional de Ciencias de la Computación, Avances en Ciencias de la Computación, págs. 103-108, Apizaco, Tlax. México, Septiembre, 2003.

88. Miguel Morales-Sandoval, Moisés Pérez-Gutiérrez, Claudia Feregrino-Uribe, Miguel Arias-Estrada, Arquitectura FPGA para un Procesador Matricial, ENC 2003, IV Congreso Internacional de Ciencias de la Computación, Avances en Ciencias de la Computación, págs. 91-96, Apizaco, Tlax. México, Septiembre, 2003.

89. Marco Aurelio Nuño Maganda, Miguel Arias Estrada, Claudia Feregrino Uribe, Implementación Hardware de Aplicaciones de la Pirámide, ENC 2003, IV Congreso Internacional de Ciencias de la Computación, Avances en Ciencias de la Computación, págs. 83-89, Apizaco, Tlax. México, Septiembre, 2003.

2001


90. Feregrino C. y Jones S. Optimisation of PPMC Model for Hardware Implementation, Proceedings of the 2001 Euromicro Symposium on Digital Systems Design (DSD'01), IEEE Computer Society Press, ISBN 0-7695-1239-9. págs. 120 - 126, Varsovia, Polonia, Septiembre, 2001.

1999

91. Nunez J.L., Feregrino C. Bateman S. y Jones S., The X-MatchLITE FPGA-Based Data Compressor, Proceedings of the 25th EUROMICRO Conference, Digital Systems Design: Architectures, Methods and Tools, IEEE Computer Society ISBN 0-7695-0321-7 , págs. 126-132, Milan, Italia, Septiembre, 1999.

92. Nunez J.L., Feregrino C., Bateman S. y Jones S., The X-MatchLITE FPGA-based data compressor, Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, Monterey, California, Estados Unidos, Febrero, 1999.

Patents